1. Field of the Invention
The present invention relates to a bus control system and method of controlling a bus to which two or more devices are connected. Especially, the present invention relates to a bus control system and a method of controlling a bus by using a bus control device having two or more bus controllers, when the device connected to the bus uses a bus.
This application relies for priority on Japanese patent application, Serial Number 245256/2001, filed Aug. 13, 2001, which is incorporated herein by reference in its entirety.
2. Description of the Related Art
The system having one bus line (for example, external bus line) to which two or more devices or apparatus, such as ROM, SRAM and DRAM are connected has been known in this technical field. In this system, a signal, such as a control command, an address, data, etc. output from CPU or a control device, is transferred to each device through the bus line shared between two or more devices.
When two or more deices share one bus line, the devices cannot use the bus line simultaneously. Therefore, use of the bus line is adjusted within a bus control device (or use of the bus line is arbitrated.). In detail, use of the bus line is controlled by controlling operation of two or more bus controllers corresponding to two or more devices. Generally, when a bus use request signal is outputted from two or more bus controllers, a priority is given to these bus use request signals. Grant of using the bus line (grant of bus use request signals) is given to each bus controller according to this priority. The device which gives use permission of the bus line to each bus controller and which sets priority to the bus use request signal output from each bus controller is called a bus arbiter.
FIG. 1 is a block diagram showing an outline structure of a conventional bus control device.
External bus EXBUS is connected to an external bus control device 1. Two or more devices or apparatuses which are not illustrated, such as ROM, SRAM, and DRAM, are connected to the external bus EXBUS.
The external bus control device 1 has a central processing unit (CPU) 11, a first external bus controller 12, a second external bus controller 13, and an external bus arbiter 14.
The central processing unit (CPU) 11 outputs an address signal to the above mentioned device. Moreover, the CPU 11 transmits data to these devices and receives data from these devices. Furthermore, the CPU11 issues an access request to each devices or apparatus. Moreover, the CPU11 receives an end notice of access against each device.
The first external bus controller 12 and the second external bus controller 13 convert a signal outputted from the CPU 11 so that a signal outputted from the CPU 11 may be transferred on the external bus EXBUS.
An external bus arbiter 14 sets up a priority to external bus use request signals outputted from the external bus controller 12 and the second external bus controller 13. And the external bus arbiter 14 outputs a use permission signal of the external bus EXBUS to one of the external bus controllers. Thereby, adjustment (arbitration) is carried out among the bus use request signals.
Moreover, a reset signal RST for initialization and a clock signal CLK used as the base signal of control timing is inputted into each block 11 through 14 illustrated in FIG. 1.
The first external bus controller 12 is a controller which outputs the external bus use request signal based on only the CPU 11. In other words, the first external bus controller 12 is an external bus controller which outputs the external bus use request signal synchronizing with operation of the CPU 11. Hereinafter, such an external bus controller is called an external bus controller of a passive type.
The first external bus controller 12 has a CPU side interface I/F 21 which is an interface part with the CPU 11, and an arbiter side interface I/F22 which is an interface part with the external bus arbitor 14.
In the arbiter side I/F 22, an off-time memory part 31 which stores a value of an off-time period for avoiding that data read-out operation of ROM, SRAM, and DRAM, etc. competes at the external bus EXBUS is provided. The value of the off-time period depends on the types of devices (apparatus) and its operation speed.
The CPU side I/F 21 receives an address signal ADR from the CPU 11, and an access request signal ARQ. Moreover, the CPU side I/F 21 output an access end signal AED1 to the CPU 11. Furthermore, the CPU side I/F 21 transmits data DAT to the CPU11, and receives data DAT from the CPU 11.
Moreover, the CPU side I/F 21 transmits a read-out request BRQ1 and a write-in request WRQ1 to the arbiter side I/F 22, and receive an external bus access end signal DED1 from the arbiter side I/F 22.
The arbiter side I/F 22 transmits an address signal ADR1, a data enable signal DEN1, an external bus use request signal BRQ1, and a data signal DAT1 to the external bus arbiter 14, and receives a data signal DAT1 and an external bus use permission signal BAM1 from the external bus arbiter 14. In addition, each off-time data stored in the off-time memory part 31 shows an extended time period of the external bus use request signal BRQ1 at the time of an end of access to one address. By providing this off-time period, it is prevented that competition of data read-out operation etc. occurs between the present access and next access among the devices connected to the external bus.
The second external bus controller 13 is a controller which can output the external bus use request based on operation of the CPU 11, and a spontaneous external bus use request. The spontaneous external bus use request is a request issued at predetermined interval based on the request from the device connected to the external bus EXBUS like DRAM for which refreshment is needed. In other words, the second external bus controller 13 is a controller which can also output the external bus request signal asynchronously with operation of the CPU 11. Hereinafter, such an external bus controller is called an external bus controller of passive type/spontaneous type.
The second external bus controller 13 has a CPU side interface I/F 41 which is an interface part with CPU 11, and an arbiter side interface I/F 42 which is an interface part with the external bus arbiter 14. In the arbiter side interface I/F42, an off-time memory part 51 which stores a value of an off-time period for avoiding that data-read out operation of ROM, SRAM, DRAM, etc. competes at the external bus EXBUS, and a spontaneous request generation part 52 which generates a spontaneous external bus use request are provided.
The CPU side interface I/F41 receive an address signal ADR from the CPU 11, and an access request signal ARQ. Moreover, the CPU side interface I/F 41 transmits an access end signal AED2 to CPU 11. Furthermore, the CPU side interface I/F 41 transmits a data DAT to the CPU 11, and receives a data DAT from the CPU 11.
Moreover, the CPU side interface I/F 41 transmits a read-out request RRQ2 and a write-in request WRQ2 to the arbiter side interface I/F42, and receives an external bus access end signal DED2 from the arbiter side interface I/F 42.
The arbiter side interface I/F42 transmits address signal ADR2, a data enable signal DEN2, an external bus use request signal BRQ2, and a data signal DAT2 to the external bus arbiter 14, and receives a data signal DAT2 and an external bus use permission signal BAM2 from the external bus arbiter 14. Moreover, the external bus use request signal BRQ2 is transmitted also to the first external bus controller 12, while it is transmitted to the external bus arbiter 14.
Each off-time data stored in the off-time memory part 51 shows the extended time period of the external bus use request signal BRQ2 at the time of an end of access to one address like the off-time memory part 31. By providing this off-time period, it is prevented that competition of date read-out operation etc. occurs between the present access and next access, between the devices connected to the external bus EXBUS.
The spontaneous request generated in the spontaneous request generation part 52 is a refreshment request to DRAM, when the device connected to the external bus EXBUS is DRAM. For every predetermined refresh cycle period, this request is not based on a request from the CPU, but is generated from the spontaneous request generation part 52.
FIG. 2 is a timing chart in case the second external bus controller 13 transmits the external bus use request signal BRQ2 synchronizing with operation of the CPU. In FIG. 2, each processing is performed in response to the clock timing of T1-T15, for example.
In FIG. 2, (a) denotes the clock signal CLK supplied to each block of the external bus control device 1, (c) denotes the address signal ADR outputted from the CPU 11 to the first external bus controller 12 and the second external bus controller 13, and (d) denotes the access request signal ARQ outputted from the CPU 11 to the first external bus controller 12 second external bus controller 13.
Moreover, (e) denotes the access end signal AED1 which shows an end of access by the first external bus controller 12, (f) denotes the address signal ADR1 outputted from the external bus controller 12 to the external bus arbiter 14, (g) denotes the data DAT 1 outputted and inputted between the first external bus controller 12 and the external bus arbiter 14, (h) denotes the external bus use request signal BRQ1 outputted to the external bus arbiter 14 from the first external bus controller 12, and (i) denotes the external bus use permission signal BAM1 outputted to the external bus controller 12 from the external bus arbiter 14.
In FIG. 2, (l) denotes the access end signal AED2 which shows an end of access according to the second external bus controller 13, (m) denotes the address signal ADR2 outputted to the external bus arbiter 14 from the second external bus controller 13, (n) denotes the data DAT 2 outputted and inputted between the second external bus controller 13 and the external bus arbiter 14, and (o) denotes the external bus use request signal BRQ2 outputted to the external bus arbiter 14 from the second external bus controller 13. (p) denotes the external bus use permission signal BAM2 outputted to the second external bus controller 13 from the external bus arbiter 14.
Moreover, (r) denotes the address signal ADRX transmitted to the external bus EXBUS from the external bus arbiter 14, and (s) denotes the data signal DATX transmitted and received between the external bus arbiter 14 and the external bus EXBUS.
Next, operation of the external bus control device 1 in case the second external bus controller 13 transmits the external bus use request signal BRQ2 synchronizing with operation of the CPU is explained. (This operation is called the first mode.)
Here, it is assumed that the first SRAM and second SRAM are connected to the external bus EXBUS. The address signal A1 is an address which specifies the first SRAM, and the address signal A2 is an address which specifies the second SRAM. In addition, the first external bus controller 12 performs transmission and reception of data to this first SRAM, and the second external bus controller 13 performs transmission and reception of data to this second SRAM.
First, the CPU 11 outputs the address signal A1 to the first external bus controller 12 as the address signal ADR. Furthermore, the CPU 11 outputs the access request signal ARQ having an H level. Access to the first SRAM is started after this. In addition, when this access is the write-in operation to the first SRAM, the write-in request WRQ1 is outputted, and when this access is read-out operation to the first SRAM, the read-out request RRQ1 is outputted. However, explanation is omitted about these requests. (time period T1)
The first external bus controller 12 outputs the external bus use request signal BRQ1 having the H level in response to the access request signal ARQ having the H level. (time period T2)
Next, the external bus arbiter 14 detects that the external bus use request signal BRQ2 of the H level does not exist, in response to the H level of the external bus use request BRQ1, and responses the external bus use permission signal BAM1 having the H level to the first external bus controller 12. Furthermore, the first external bus controller 12 outputs the address signal A1 to the external bus arbiter 14 as the address signal ADR1. Furthermore, the first external bus controller 12 outputs the data signal D1 to the external bus arbiter 14 as the data signal DAT1. The address signal A1 is outputted to the external bus EXBUS as the address signal ADRX and the data signal D1 is outputted to the external bus EXBUS as the data signal DATX based on the transition of the L level to the H level of the external bus use permission signal BAM1. (time period T3)
After that, for example, read-out operation from the first SRAM is performed.
Next, after the access to the first SRAM is completed, the first external bus controller 12 outputs the access end signal AED1 having the H level to the CPU 11. The CPU 11 receives the access end signal AED1 having the H level, and outputs again the access request signal ARQ having H level. The H level of the access request signal ARQ indicates that the following access cycle is started. Moreover, the CPU 11 outputs an address signal A2 to the second bus controller 13 as the address signal ADR in order to start access against the second SRAM in the following cycle. (time period T11)
Next, the second bus controller 13 outputs the external bus request signal BRQ2 having the H level in response to the access request signal ARQ having the H level. In addition, although access to the first SRAM is ended, the H revel of the access request signal BRQ1 is maintained during the off-time period stored in the off-time memory part 31 about the first SRAM. (time period T12)
Next, the external bus arbiter 14 detects that the external bus use request signal BRQ1 is still the H level, and makes the L level of the external bus use permission signal BAM2 maintain. On the other hand, since the off-time period expired, in this time period T13, the H level of the access request signal BRQ1 changes to the L level. (time period T13)
Next, the external bus arbiter 14 detects that the external bus use request signal BRQ1 changes to the L level and responses the external bus use permission signal BAM2 having the H level to the second external bus controller 13 in response to the external bus use request signal BRQ2 having the H level. Moreover, the external bus arbiter 14 changes the H level of the external bus use permission signal BAM1 to the L level in response to the external bus use request signal BRQ1 having the L level.
Furthermore, the second external bus controller 13 outputs the data signal D2 to the external bus arbiter 14 as the data signal DAT2. The address signal A2 is outputted to the external bus EXBUS as the address signal ADRX and the data signal D2 is outputted to the external bus EXBUS as the data signal DATX based on the transition of the L level of the external bus use permission signal BAM2 to the H level. Access to the second SRAM is started after this. That is, it means that the right for using the external bus EXBUS had moved from the first external bus controller 12 to the second external bus controller 13. (time period T14)
FIG. 3 is a flow chart which shows the outline of operation of the external bus control device 1 which has the second external bus controller 13 which transmits the external bus use request signal BRQ2 synchronizing with operation of the CPU. That is, FIG. 3 is the summary of explanation of operation of the first above-mentioned mode.
The external bus use request signal BRQ1 is outputted. (Step S1)
The external bus use permission signal BAM1 is outputted. (Step S2)
Whether the first external bus controller 12 has ended use of the external bus EXBUS is judged. (Step S3)
When the first external bus controller 12 has not ended use of the external bus, Step S3 is repeated. (Step S3: NO)
When the first external bus controller 12 ends use of the external bus, the external bus use request signal BRQ1 is extended by the off-time. (Step S4)
The external bus use request signal BRQ2 is outputted. (Step S5)
Whether the output of the external bus use request signal BRQ1 extended at Step S4 is completed is judged. (Step S6)
When the output of the external bus use request signal BRQ1 is not ended, Step S6 is repeated. (Step S6: NO)
When the output of the external bus use request signal BRQ1 is ended, the output of the external bus use permission signal BAM1 is stopped. (Step S7)
The external bus use permission signal BAM2 is outputted. (Step S8)
As mentioned above, the second external bus controller 13 which outputs the external bus use request signal BRQ2 synchronizing with operation of the CPU 11 is explained by FIG. 2 and FIG. 3.
Subsequent explanation explains the case where the second external bus controller 13 outputs the external bus use request signal BRQ2 asynchronously with operation of the CPU 11. (This operation is called a second mode.)
That is, the second external bus controller 13 outputs spontaneously the external bus use request BRQ2 for a refreshment request of DRAM connected to the external bus EXBUS.
Here, DRAM is connected to the external bus EXBUS instead of the second SRAM. Therefore, the address signal A2 is an address which specifies DRAM. In addition, the second external bus controller 13 performs transmission and reception of data to this DRAM.
FIG. 4 is a timing chart in case the second external bus controller 13 transmits spontaneously the external bus use request signal BRQ2.
The main differences between FIG. 4 and FIG. 2 are as follows.
(1) The access request to the first SRAM is issued continuously. That is, in the time period T11, the address signal ADR which the CPU11 outputs is the address signal A1 following on the last cycle.
(2) The bus use request signal BRQ2 is set to the H level independently of the access request signal ARQ in the time period T5. This corresponds to Step S13 in FIG. 5.
(3) The access request signal BRQ1 is again set to the H level in the time period T14. This corresponds to Step S19 in FIG. 5.
In this second mode, the external bus use request signal BRQ2 is outputted asynchronously with the access request signal ARQ which the CPU 11 outputs. (The external bus use request signal BRQ2 enters into an active state asynchronously with the CPU 11.)
Such an access request has a possibility of being ignored when as follows. That is, as shown in FIG. 4, it is in the case where the CPU 11 tries to access the first SRAM in two continuous cycles.
In such a case, the H level of the external bus use request signal BRQ1 is maintained according to the address A1 outputted from the CPU 11, as shown by the dotted line indicated by an arrow A in FIG. 4. Consequently, in the following cycle, the first SRAM is accessed again and an access to DRAM is ignored. As a result, data of DRAM may be destroyed.
In this second mode, in order to receive an access request signal BRQ2, whenever access is completed, the level of the external bus use request signal BRQ1 is changed to the L level. That is, the external bus use request signal BRQ1 is compulsorily set as the L level after the off-time period so that the access request signal BRQ2 may be received. Thereby, the external bus use permission is moved from the external bus controller 12 to the external bus controller 13.
As mentioned above, in the conventional external bus control device 1, especially in order to perform the second mode, the first external bus controller 12 supervise (monitors) the external bus use request signal BRQ2 outputted from the second external bus controller 13.
However, in the above-mentioned conventional external bus control device, when newly adding an external bus controller (it corresponds to the second external bus controller.) of a passive type/spontaneous type, the external bus use request signal of this passive type external bus controller needs to be made to input into all other external bus controllers (it corresponds to the first external bus controller.). Therefore, in other external controllers, new circuit designing for receiving this external bus use request signal is needed. This new designing needs to be changed whenever the number of the external bus controllers which should be added is changed (i.e., whenever the number of the devices connected to the external bus EXBUS is changed).
Therefore, it is difficult to shorten the manufacture period of the system containing the external bus control device. Thereby, the subject that replying to a user's needs immediately become difficult occurs.
Moreover, when the external bus controller (it corresponds to the second external bus controller.) of a passive type/spontaneous type is deleted and the CPU accidentally specified an address which corresponds to this external bus controller, other subjects that a system carry out a stack occurs.
Therefore, in the conventional external bus control device, an addition and deletion of an external bus controller is not easy.
The present invention is made in order to solve the above-mentioned subject, and one object of the present invention is to provide a bus control system and a bus control method of carrying out easily an addition and deletion of the external bus controller in an external bus control device.